1. Field of the Invention
The present invention relates to a pixel, an organic light emitting display using the pixel circuit and a driving method, and more particularly, to a pixel and an organic light emitting display using the pixel and a driving method capable of displaying an image of desired luminance
2. Description of the Related Art
Various flat panel displays have been developed so as to have less weight and bulk than that of a cathode ray tube (CRT). Flat panel displays include liquid crystal displays (LCDs), field emission displays (FEDs), plasma display panels (PDPs), organic light emitting displays, etc. An organic light emitting display presents an image using organic light emitting diodes that generate light from the recombination of electrons and holes. Such an organic light emitting display has advantages in that it has a high response speed, and operates in a low power consumption.
FIG. 1 is a circuit view showing a conventional organic light emitting display. With reference to FIG. 1, a pixel 10 of the conventional organic light emitting display includes an OLED, and a pixel circuit 12 for providing a current to the OLED. An anode of the OLED is connected to the pixel circuit 12, and a cathode is connected to the second power source ELVSS. This OLED generates a luminance corresponding to a current provided from the pixel circuit 12.
The pixel circuit 12 controls a quantity of current that is provided from the first power source ELVDD to the OLED in response to a data signal which is provided from a data line Dm. To accomplish this, the pixel circuit 12 includes the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the first capacitor C1, and the second capacitor C2. A gate of the first transistor M1 is connected to the n (n is a positive integer)-th scan line Sn, and the first electrode is connected to the m (m is a positive integer)-th data line Dm. And, the second electrode of the first transistor M1 is connected to the first node N1. The first transistor M1 is turned-on when a scan signal is provided to the n-th scan line Sn, such that a data signal provided from the data line Dm is provided to the first node N1. On the other hand, the first electrode is set as either a source or a drain, and the second electrode is set as the other. For example, the first electrode is set as the source and the second electrode is set as the drain.
The gate of the second transistor M2 is connected to the second node N2, and the first electrode of the second transistor M2 is connected to the first power source ELVDD. The second electrode of the second transistor M2 is connected to the first electrode of the fifth transistor M5. The second transistor M2 provides the first electrode of the fifth transistor M5 with a current corresponding to a voltage provided to the second node N2.
The gate of the third transistor M3 is connected to the (n−1)-th scan line Sn−1, and the first electrode of the third transistor M3 is connected to the first power source ELVDD. The second electrode of the third transistor M3 is connected to the first node N1. Therefore, the third transistor M3 is turned on to allow the first power source ELVDD to be electrically connected to the first node N1 when a scan signal is provided to the (n−1)-th scan line Sn−1.
The gate of the fourth transistor M4 is connected to the (n−1)-th scan line Sn−1, and the first electrode of the fourth transistor M4 is connected to the second node N2. The second electrode of the fourth transistor M4 is connected to the first electrode of the fifth transistor M5. Therefore, the fourth transistor M4 is turned on so as to allow the second node N2 to be electrically connected to the first electrode of the fifth transistor M5 when a scan signal is provided to the (n−1)-th scan line Sn−1.
The gate of the fifth transistor M5 is connected to the (n−1)-th scan line Sn−1, and the first electrode of the fifth transistor M5 is connected to the second electrode of the second transistor M2. The second electrode of the fifth transistor M5 is connected to an OLED. Therefore, the fifth transistor M5 is turned off when the scan signal is provided to the (n−1)-th scan line Sn−1 and turned on when not, such that a current from the second transistor M2 flows to the OLED. Accordingly, the fifth transistor M5, which has a different type than the third and fourth transistors M3 and M4, is used. For example, if the third and fourth transistors M3 and M4 are PMOS, the fifth transistor M5 is NMOS. The first capacitor C1 is charged to a voltage corresponding to a data signal via the first transistor M1 while the scan signal is provided to the n-th scan line Sn.
FIG. 2 is a timing diagram showing driving waveforms provided to the scan lines and data line depicted in FIG. 1. Hereinafter, the operation of the pixel 10 will be explained by reference to FIG. 1 and FIG. 2. Referring to FIG. 2, a scan signal is provided to the (n−1)-th scan line Sn−1, and a data signal is provided to the m-th data line Dm. When the scan signal is provided to the (n−1)-th scan line Sn−1, the third and fourth transistors M3 and M4 are turned on, and the fifth transistor M5 is turned off. The first node N1 is electrically connected to the first power source ELVDD when the third transistor M3 is turned on. The second node N2 is electrically connected to the first electrode of the second transistor M2 when the fourth transistor M4 is turned on. A voltage difference between the first node N1 and the second node N2 corresponding to a threshold voltage of the second transistor M2 is charged across the second capacitor C2. Also, when the fifth transistor M5 is turned off, current is not provided to the OLED. And, since the first transistor M1 is off while the scan signal is provided to the (n−1)-th scan line Sn−1, the data signal which is provided to the m-th data line Dm is not provided to the pixel circuit 12. Thus, the first node N1 is initialized to the voltage of the first power supply ELVDD, and the second node N2 is initialized to the voltage of the first power supply ELVDD minus a threshold voltage of the second transistor M2.
Then, the scan signal is provided to the n-th scan line Sn, and the data signal is provided to the m-th data line Dm. When the scan signal is provided to the n-th scan line Sn, the first transistor M1 is turned on, and the data signal on to the m-th data line Dm is provided to the first node N1. At this time, the first capacitor C1 is charged to a voltage that corresponds to a difference between the voltage of the first power supply ELVDD and the voltage of the data signal applied to the first node N1.
Thereafter, the second transistor M2 controls the quantity of current which flows into the OLED through the fifth transistor M5 according to the voltage across the first and second capacitors C1 and C2. The OLED emits light with brightness corresponding to the quantity of current that is provided from the second transistor M2.
However, it is a problem that the prior art pixel 10 can not display an image having a desired brightness because of a kickback phenomenon. When the fourth transistor M4 is turned off, an electric charge of a parasitic capacitor between the gate and the first power source is redistributed, such that a kickback voltage is generated. Some of the charge that is generated from the fourth transistor M4 goes to the second node N2 and changes the voltage of the second node N2. When the voltage of the second node N2 is changed, the voltage of the first node N1 is also changed, resulting in the voltage across the first capacitor C1 changing. Accordingly, the voltages at the first node N1 and the second node N2 are disturbed and are not the desired initialization voltages discussed above. This disturbance affects the current supplied to the OLED, and therefore the brightness. Because the magnitude of the disturbance is affected by such factors as the capacitance values of the gate-source capacitor of the fourth transistor M4 and the parasitic capacitors on the second node N2, which vary from pixel to pixel, the current and brightness also varies from pixel to pixel.
Also, in the prior art pixel 10, the first capacitor C1 is charged to a voltage corresponding to a difference between the voltage of the first power source ELVDD and the voltage of the data signal. Therefore, when charging the first capacitor C1 with a desired voltage, the first power source ELVDD should be held constant. However, the voltage of the first power source ELVDD tends to vary according to the position of each of the pixels 10 in an array. Therefore, the first capacitors C1 of each of the pixels across the array are not consistently charged to the desired voltage. In other words, because the voltage value is set according to the position of each of the pixels 10 in the array, an image is not displayed with a uniform brightness in the prior art.